| 2023-12 |
Unified Wear-Leveling Technique for NVM-Based Buffer of SSD |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2023-08 |
Operand-Oriented Virtual Memory Support for Near-Memory Processing |
IEEE Transactions on Computers
|
| 2023-04 |
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
|
| 2022-05 |
STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2021-12 |
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks |
IEEE Embedded Systems Letters
|
| 2021-11 |
Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection |
IEEE Access
|
| 2021-05 |
Cross-Corner Delay Variation Model for Standard Cell Libraries |
IEEE Access
|
| 2020-10 |
Multitoken-Based Power Management for NAND Flash Storage Devices |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2020-02 |
Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2019-08 |
A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-03 |
A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2019-02 |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
MICROMACHINES
|
| 2018-09 |
ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2018-02 |
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2018-01 |
EXTREME : Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2017-05 |
Scalable bandwidth shaping scheme via adaptively managed parallel heaps in manycore-based network processors |
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
|
| 2017-05 |
An effective pre-store/pre-load method exploiting intra-request idle time of NAND flash-based storage devices |
MICROPROCESSORS AND MICROSYSTEMS
|
| 2016-06 |
DHL-cache: dynamic per history length adjustment for low-power L2 cache |
ELECTRONICS LETTERS
|
| 2016-02 |
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-01 |
TLC 낸드 플래시기반 저장 장치에서 페이지 중복쓰기 기법을 이용한 SLC 버퍼 성능향상 연구 |
전자공학회논문지
|
| 2016-01 |
낸드 플래시 기반 저장장치의 피크 전류 모델링을 이용한 전력 최적화 기법 연구 |
전자공학회논문지
|
| 2014-08 |
C-Lock: Energy Efficient Synchronization for Embedded Multicore Systems |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2014-06 |
Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2014-05 |
An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2014-03 |
Design of a bitmap-based QoS-aware memory controller for a packet memory |
IEICE ELECTRONICS EXPRESS
|
| 2014-01 |
An energy and performance efficient DVFS scheme for irregular parallel divide-and-conquer algorithms on the intel SCC |
IEEE COMPUTER ARCHITECTURE LETTERS
|
| 2013-09 |
GPU-based acceleration of an RNA tertiary structure prediction algorithm |
COMPUTERS IN BIOLOGY AND MEDICINE
|
| 2013-08 |
캐시 버퍼와 읽기 요청을 고려한 낸드 플래시 기반 솔리드 스테이트 디스크의 요청 스케줄링 기법 |
전자공학회논문지
|
| 2013-08 |
Application-aware Design Parameter Exploration of NAND Flash Memory |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2013-05 |
논리 블록의 접근경향을 활용한 이종 낸드 플래시 기반 저장장치를 위한 Flash Translation Layer |
전자공학회논문지
|
| 2013-05 |
Power failure protection scheme for reliable high-performance solid state disks |
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
|
| 2013-04 |
A low-power packet memory architecture with a latency-aware packet mapping method |
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
|
| 2013-03 |
Page overwriting method for performance improvement of NAND flash memories |
IEICE ELECTRONICS EXPRESS
|
| 2013-01 |
Mixed Integer Linear Programming을 이용한 온칩 크로스바 네트워크 토폴로지 합성 |
전자공학회논문지
|
| 2012-09 |
Analytical memory bandwidth model for many-core processor based systems |
IEICE ELECTRONICS EXPRESS
|
| 2012-09 |
Application-Support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2012-01 |
Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2010-09 |
Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning |
Computer Journal
|
| 2010-08 |
Energy-Optimal Dynamic Thermal Management: Computation and Cooling Power Co-Optimization |
IEEE Transactions on Industrial Informatics
|
| 2010-07 |
Architecture Exploration of High-Performance PCs with a Solid-State Disk |
IEEE Transactions on Computers
|
| 2010-06 |
A fast and simple system performance emulator for enhanced solid state disks: a case study of long read operations |
JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE C-COMPUTERS & ELECTRONICS
|
| 2010-04 |
On the Thermal Attack in Instruction Caches |
IEEE Transactions on Dependable and Secure Computing
|
| 2010-03 |
NAND Flash Memory 기반 저장장치 및 기술 동향 |
전자공학회지
|
| 2009-11 |
Fast performance analysis of NAND flash-based storage device |
Electronics Letters
|
| 2009-09 |
K-maximin clustering: A maximin correlation approach to partition-based clustering |
IEICE Electronics Express
|
| 2009-09 |
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2009-08 |
Design and Analysis of Flash Translation Layers for Multi-Channel NAND Flash-based Storage Devices |
IEEE Transactions on Consumer Electronics
|
| 2009-08 |
High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2009-06 |
Topology Synthesis of Cascaded Crossbar Switches |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2009-05 |
A robust peak detection method for RNA structure inference by high-throughput contact mapping |
Bioinformatics
|
| 2009-04 |
Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs |
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
|
| 2009-02 |
Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
|
| 2008-12 |
PC향 SSD의 성능 분석을 위한 트랜잭션 수준 시뮬레이터 |
전자공학회논문지 - SD
|
| 2008-12 |
온도 인지 마이크로프로세서를 위한 듀얼 레지스터 파일 구조 |
정보과학회논문지 : 시스템 및 이론
|
| 2008-11 |
Research Challenges in Many-core SoC Designs |
한국통신학회지 (정보와 통신)
|
| 2008-11 |
Energy and Performance Optimization of Demand Paging with OneNAND Flash |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2008-08 |
Adopting the banked register file scheme for better performance and less leakage |
ETRI Journal
|
| 2008-07 |
Adopting the drowsy technique for instruction caches: A soft error perspective |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
|
| 2008-05 |
Extended MPEG video format for efficient Dynamic Voltage Scaling |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
|
| 2008-03 |
Scalable QoS-aware memory controller for high-bandwidth packet memory |
IEEE Transactions on Very Large Scale Integration (Vlsi) Systems
|
| 2007-05 |
Clustering protein environments for function prediction: finding PROSITE motifs in 3D |
BMC BIOINFORMATICS
|
| 2007-04 |
Scenario-aware bus functional modeling for architecture-level performance analysis |
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
|
| 2007-03 |
지연 이중 버퍼링: OneNAND 플래시를 이용한페이지 반입 비용 절감 기법 |
전자공학회논문지 - SD
|
| 2007-03 |
Latency-aware bus arbitration for real-time embedded systems |
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
|
| 2006-11 |
Variability-insensitive scheme for NAND flash memory interfaces |
ELECTRONICS LETTERS
|
| 2005-12 |
System Level Architecture Evaluation and Optimization: an Industrial Case Study with AMBA3 AXI |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2005-12 |
An Industrial Case Study of the ARM926EJ-S Power Modeling |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2005-06 |
ViP: A Practical Approach to Platform-based System Modeling Methodology |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2003-09 |
플랫폼을 기반으로 하는 SoC 설계 방법 |
전자공학회논문지
|
| 2002-11 |
Dynamic Power Management for Non-stationary Service Requests |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2002-09 |
Value-sensitive Automatic Code Specialization for Embedded Software |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2002-04 |
Value-based Source Code Specialization for Energy Reduction |
ST Journal of System Research
|